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data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 83905-01 revision 1 05/01/15 1 ?2015 integrated device technology, inc. general description the 83905-01 is a low skew, 1-to-6 lvcmos fanout buffer. the low impedance lvcmos outputs are designed to drive 50 ? series or parallel terminated transmission lines. the effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. the 83905-01 is characterized at full 1.8v, 1.5v, and 1.2v, mixed 1.8v/1.5v, 1.8v/1.2v and 1.5v/1.2v output operating supply mode. guaranteed output skew characteristics along with the 1.2v output capabilities makes the 83905-01 ideal for high performance, single ended applications that also requ ire a limited output voltage. pin assignments features ? six lvcmos outputs ? outputs able to drive 12 series terminated lines ? crystal oscillator interface ? crystal input frequency range: 10mhz to 40mhz ? output skew: 95ps (maximum) ? rms phase jitter @ 25mhz, (100hz ? 1mhz): 0.17ps (typical) offset noise power 100hz................. -115 dbc/hz 1khz ................... -138 dbc/hz 10khz ................. -154 dbc/hz 100khz ............... -160 dbc/hz ? synchronous output enables ? power supply modes: full 1.8v, 1.5v, 1.2v mixed 1.8v core/1.5v output operating supply mixed 1.8v core/1.2v output operating supply mixed 1.5v core/1.2v output operating supply ? 0c to 70c ambient operating temperature ? available in lead-free (rohs 6) package block diagram 20-pin, 4mm x 4mm vfqfn package 83905-01 gnd gnd bclk4 v ddo bclk5 gnd gnd bclk2 v dd bclk3 6 7 8910 20 19 18 17 16 enable2 xtal_out nc enable1 xtal_in bclk1 v ddo bclk0 gnd gnd 2 3 4 5 1 15 14 13 12 11 83905-01 16-pin, 4.4mm x 5.0mm tssop package bclk4 v ddo bclk5 enable1 xtal_in v dd bclk3 gnd v ddo bclk0 gnd enable2 xtal_out bclk2 gnd bclk1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 synchronize synchronize bclk0 bclk1 bclk2 bclk3 bclk4 bclk5 xtal_in xtal_out enable 1 enable 2
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 2 revision 1 05/01/15 pin descriptions and characteristics table 1. pin descriptions table 2. pin characteristics function table table 3. clock enable function table figure 1. enable timing diagram name type description xtal_out output crystal oscillator interface. xtal_in input crystal oscillator interface. enable1, enable2 input clock enable. lvcmos/lvttl interface levels. see table 3. bclk0, bclk1, bclk2, bclk3, bclk4, bclk5 output clock outputs. lvcmos interface levels. gnd power power supply ground. v dd power power supply pin. v ddo power output supply pin. nc unused no connect. symbol parameter test conditions minimum typical maximum units c in input capacitance enable[2:1] 4 pf c pd power dissipation capacitance (per output) v ddo = 2.0v 12 pf v ddo = 1.6v 12 pf v ddo = 1.26v 12 pf r out output impedance v ddo = 1.8v 0.2v 17 ? v ddo = 1.5v 0.1v 18 ? v ddo = 1.2v 5% 24 ? control inputs outputs enable 1 enable2 bclk[0:4] bclk5 0 0 low low 0 1 low toggling 1 0 toggling low 1 1 toggling toggling bclk5 bclk[0:4] enable2 enable1
revision 1 05/01/15 3 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 1.8v 0.2v, t a = 0c to 70c note 1: measured with outputs unterminat ed, and xtal_in and xtal_out floated. table 4b. power supply dc characteristics, v dd = v ddo = 1.5v 0.1v, t a = 0c to 70c note 1: measured with outputs unterminat ed, and xtal_in and xtal_out floated. table 4c. power supply dc characteristics, v dd = v ddo = 1.2v 5%, t a = 0c to 70c note 1: measured with outputs unterminat ed, and xtal_in and xtal_out floated. item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v input, v i crystal oscillator input 0v to v dd outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, t j 125 ? c storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 1.6 1.8 2.0 v v ddo output supply voltage 1.6 1.8 2.0 v i dd ; note 1 power supply current enable [1:2] = 00 4 10 ma i ddo ; note 1 output supply current enable [1:2] = 00 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 1.4 1.5 1.6 v v ddo output supply voltage 1.4 1.5 1.6 v i dd ; note 1 power supply current enable [1:2] = 00 3 7 ma i ddo ; note 1 output supply current enable [1:2] = 00 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 1.14 1.2 1.26 v v ddo output supply voltage 1.14 1.2 1.26 v i dd ; note 1 power supply current enable [1:2] = 00 2 6 ma i ddo ; note 1 output supply current enable [1:2] = 00 1 ma
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 4 revision 1 05/01/15 table 4d. power supply dc characteristics, v dd = 1.8v 0.2v, v ddo = 1.5v 0.1v, t a = 0c to 70c note 1: measured with outputs unterminat ed, and xtal_in and xtal_out floated. table 4e. power supply dc characteristics, v dd = 1.8v 0.2v, v ddo = 1.2v 5%, t a = 0c to 70c note 1: measured with outputs unterminat ed, and xtal_in and xtal_out floated. table 4f. power supply dc characteristics, v dd = 1.5v 0.1v, v ddo = 1.2v 5%, t a = 0c to 70c note 1: measured with outputs unterminat ed, and xtal_in and xtal_out floated. table 4g. lvcmos/lvttl dc characteristics, t a = 0c to 70c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information, output load test circuit diagrams. symbol parameter test conditions minimum typical maximum units v dd power supply voltage 1.6 1.8 2.0 v v ddo output supply voltage 1.4 1.5 1.6 v i dd ; note 1 power supply cu rrent enable [1:2] = 00 4 10 ma i ddo ; note 1 output supply current enable [1:2] = 00 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 1.6 1.8 2.0 v v ddo output supply voltage 1.14 1.2 1.26 v i dd ; note 1 power supply current enable [1:2] = 00 4 10 ma i ddo ; note 1 output supply current enable [1:2] = 00 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 1.4 1.5 1.6 v v ddo output supply voltage 1.14 1.2 1.26 v i dd ; note 1 power supply current enable [1:2] = 00 3 7 ma i ddo ; note 1 output supply current enable [1:2] = 00 1 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 1.8v 0.2v 1.2 v dd + 0.3 v v dd = 1.5v 0.1v 1.0 v dd + 0.3 v v dd = 1.2v 5% 0.8 v dd + 0.3 v v il input low voltage v dd = 1.8v 0.2v -0.3 0.4 v v dd = 1.5v 0.1v -0.3 0.3 v v dd = 1.2v 5% -0.3 0.2 v v oh output high voltage; note 1 v ddo = 1.8v 0.2v 0.7 v v ddo = 1.5v 0.1v 0.7 v v ddo = 1.2v 5% 0.7 v v ol output low voltage; note 1 v ddo = 1.8v 0.2v 0.4 v v ddo = 1.5v 0.1v 0.4 v v ddo = 1.2v 5% 0.4 v
revision 1 05/01/15 5 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet table 5. crystal characteristics ac electrical characteristics table 6a. ac characteristics, v dd = v ddo = 1.8v 0.2v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? ? 40mhz using a crystal input unless no ted otherwise. outputs terminated with 50 ? to v ddo /2. note 1: xtal_in can be overdriven by an external source. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: see phase noise plot. note 5: these parameters are guaranteed by design. not tested in production. parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 10 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf load capacitance 12 18 pf symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 1100mhz t sk(o) output skew; note 2, 3 90 ps tjit rms phase jitter (random); note 4 25mhz, integration range: 100hz ? 1mhz 0.17 ps t r / t f output rise/fall time 20% to 80% 300 600 ps odc output duty cycle 42 50 58 % t en output enable time; note 5 enable1 4 cycles enable2 4 cycles t dis output disable time; note 5 enable1 4 cycles enable2 4 cycles
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 6 revision 1 05/01/15 table 6b. ac characteristics, v dd = v ddo = 1.5v 0.1v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? ? 40mhz using a crystal input unless no ted otherwise. outputs terminated with 50 ? to v ddo /2. note 1: xtal_in can be overdriven by an external source. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by design. not tested in production. table 6c. ac characteristics, v dd = v ddo = 1.2v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? ? 40mhz using a crystal input unless no ted otherwise. outputs terminated with 50 ? to v ddo /2. note 1: xtal_in can be overdriven by an external source. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by design. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source; note 1 1100mhz t sk(o) output skew; note 2, 3 90 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.3 ps t r / t f output rise/fall time 20% to 80% 300 650 ps odc output duty cycle 44 50 56 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source; note 1 1100mhz t sk(o) output skew; note 2, 3 90 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.7 ps t r / t f output rise/fall time 20% to 80% 350 800 ps odc output duty cycle 44 50 56 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles
revision 1 05/01/15 7 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet table 6d. ac characteristics, v dd = 1.8v 0.2v, v ddo = 1.5v 0.1v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? ? 40mhz using a crystal input unless no ted otherwise. outputs terminated with 50 ? to v ddo /2. note 1: xtal_in can be overdriven by an external source. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by design. not tested in production. table 6e. ac characteristics, v dd = 1.8v 0.2v, v ddo = 1.2v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? ? 40mhz using a crystal input unless no ted otherwise. outputs terminated with 50 ? to v ddo /2. note 1: xtal_in can be overdriven by an external source. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by design. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source; note 1 1100mhz t sk(o) output skew; note 2, 3 90 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.18 ps t r / t f output rise/fall time 20% to 80% 300 650 ps odc output duty cycle 40 50 60 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source; note 1 1100mhz t sk(o) output skew; note 2, 3 95 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.2 ps t r / t f output rise/fall time 20% to 80% 350 800 ps odc output duty cycle 42 50 58 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 8 revision 1 05/01/15 table 6f. ac characteristics, v dd = 1.5v 0.1v, v ddo = 1.2v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? ? 40mhz using a crystal input unless no ted otherwise. outputs terminated with 50 ? to v ddo /2. note 1: xtal_in can be overdriven by an external source. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by design. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source; note 1 1100mhz t sk(o) output skew; note 2, 3 90 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.34 ps t r / t f output rise/fall time 20% to 80% 350 800 ps odc output duty cycle 42 50 58 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles
revision 1 05/01/15 9 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet typical phase noise at 25mhz (1.8v core, 1.8v output) noise power (dbc/hz) offset frequency (hz)
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 10 revision 1 05/01/15 parameter measureme nt information 1.8v core/1.8v lvcmos output load test circuit 1.2v core/1.2v lvcmos output load test circuit 1.8v core/1.2v lvcmos output load test circuit 1.5v core/1.5v lvcmos output load test circuit 1.8v core/1.5v lvcmos output load test circuit 1.5v core/1.2v lvcmos output load test circuit scope qx gnd v dd, -0.9v0.1v 0.9v0.1v v ddo scope qx gnd v dd, -0.6v5% 0.6v5% v ddo scope qx gnd v dd -0.6v5% 1.2v0.2v v ddo 0.6v5% scope qx gnd v dd, -0.75v0.05v 0.75v0.05v v ddo scope qx gnd v dd -0.75v0.05v 1.05v0.15v v ddo 0.75v0.05v scope qx gnd v dd -0.6v5% 0.9v0.07v v ddo 0.6v5%
revision 1 05/01/15 11 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet parameter measurement in formation, continued output skew output rise/fall time output enable/disable rms phase jitter output duty cycle/pulse width/period bclkx bclky t sk(b) v ddo 2 v ddo 2 20% 80% 80% 20% t r t f bclk[0:5] v dd /2 v dd /2 v ddo /2 v ol v oh 0v v dd t di s t en o u tp u t bclkx ( s ee note) oex (high-level en ab ling) t period t pw t period odc = v ddo 2 x 100% t pw bclk[0:5]
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 12 revision 1 05/01/15 application information recommendations for un used output pins outputs: lvcmos outputs all unused lvcmos output can be le ft floating. there should be no trace attached. crystal input interface the 83905-01 has been characterized with 18pf parallel resonant crystals. the capacitor val ues, c1 and c2, shown in figure 2 below were determined using an 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 2. crystal input interface xtal_in xtal_out x1 18pf parallel crystal c1 15pf c2 15pf
revision 1 05/01/15 13 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 3a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 3b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 3a. general diagram for lvcmos driver to xtal input interface figure 3b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 14 revision 1 05/01/15 schematic example figure 4 shows an example of the 83905-01 application schematic. in this example, the device is operated at v dd = v ddo = 1.8v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by an 18pf load resonant quartz crystal. the tuning capacitors c1 and c2 are fairly accurate, but minor adjustments might be re quired. for the lvcmos output drivers, two termination examples are shown in this schematic. for additional termination examples, see lvcmos termination application note. figure 4. 83905-01 schematic layout ? vddo en ab le 2 enable 1 vdd vddo zo = 50 ohm lvcmos c2 15pf r3 10 0 u1 xta l _ out 1 en ab l e 2 2 gnd 3 bc l k0 4 vd do 5 bc l k1 6 gnd 7 bc l k2 8 vdd 9 bclk3 10 gnd 11 bclk4 12 vd do 13 bclk5 14 en ab l e 1 15 xtal_in 16 c3 10uf cl = 18 pf c4 .1uf c5 .1uf r4 10 0 c1 15pf c6 .1uf r2 31 lvcmos zo = 50 ohm vdd vdd = 1. 8v vd do = 1.8v unused output s c an be left fl oati ng. there shoul d be no trac e at tached t o unus ed out puts. devi ce charac t eriz ed and specifi cat i on l imi ts set with all out put s terminat ed. optional termination
revision 1 05/01/15 15 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 83905-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 83905-01 is the sum of the core power plus the analog power plus the power dissipated due t o the load. the following is the power dissipation for v dd = 1.8v + 0.2v = 2.0v, which gives worst case results. ? power (core) max = v dd_max * i dd = 2v * 10ma = 20mw ? output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 2v / [2 * (50 ? + 17 ? )] = 14.9ma ? power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 17 ? * (14.9ma) 2 = 3.8mw per output ? total power dissipation on the r out total power (r out ) = 3.8mw * 6 = 22.8mw dynamic power dissipation at 100mhz power (100mhz) = c pd * frequency * (v dd ) 2 = 12pf * 100mhz * (2v) 2 = 4.8mw per output total power (100mhz) = 4.8mw * 6 = 28.8mw total power dissipation ? total power = power (core) max + total power (r out ) + total power (100mhz) = 20mw + 22.8mw + 28.8mw = 71.6mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature is 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100.3c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.072w *100.3c/w = 77.2c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 16-lead tssop, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 100.3c/w 96.0c/w 93.9c/w
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 16 revision 1 05/01/15 reliability information table 8a. ? ja vs. air flow table for a 16-lead tssop table 8b. ? ja vs. air flow table for a 20-lead vfqfn transistor count the transistor count for 83905-01: 505 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 57.5c/w 50.3c/w 45.1c/w
revision 1 05/01/15 17 low skew, 1:6 crystal-to-lvcmos fanout buffer 83905-01 data sheet 16-lead tssop package out line and package dimensions package outline - g suffix for 16-lead tssop table 9a. package dimensions for 16-lead tssop reference document: jede c publication 95, mo-153 all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 18 revision 1 05/01/15 20-lead vfqfn package out line and package dimensions package outline - k suffix for 20-lead vfqfn reference document: jede c publication 95, mo-220 note: the drawing and dimension data originate from idt package outline drawing psc-4170, rev03. 1. dimensions and tolerances conform to asme y14.5m-1994 2. all dimensions are in millimeter s. all angles are in degrees. 3. n is the total number of terminals. 4. all specifications comply with jedec mo-220. table 9c. package dimensions for 20-lead vfqfn all dimensions in millimeters symbol minimum nom maximum b 0.20 0.25 0.30 d 3.90 4.00 4.10 e 3.90 4.00 4.10 d2 1.95 2.10 2.25 e2 1.95 2.10 2.25 l 0.45 0.55 0.65 e 0.50 bsc n 20 a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.2 ref
83905-01 data sheet low skew, 1:6 crystal-to-lvcmos fanout buffer 19 revision 1 05/01/15 ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 83905ag-01lf 3905a01l 16-lead tssop, lead-free tube 0 ? c to 70 ? c 83905ag-01lft 3905a01l 16-lead tssop, lead-free tape & reel 0 ? c to 70 ? c 83905ak-01lf 5a01l 20-lead vfqfn, lead-free tray 0 ? c to 70 ? c 83905ak-01lft 5a01l 20-lead vfqfn, lead-free tape & reel 0 ? c to 70 ? c
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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